This invention relates to formation of lateral isolation trenches in semiconductor substrates and more particularly to enhanced methods of control of etching of the lateral trenches into which isolation dielectric is to be deposited.
Copending, commonly assigned U.S. Pat. No. 6,936,522 of An L. Steegan, Maheswaran Surendra, Hsing-Jen Wann. Ying Zhang, Franz Zach, and Robert Wong filed on 26 June 2003 entitled “Selective Silicon-on-Insulator Isolation Structure and Method” describes a method of forming Lateral isolation Regions. That method is susceptible to several non-idealities that may be encountered, when adapting it to sub-90 nm technology nodes. A potential problem with the approach described therein stems from the fact that the lateral RIE selectivity is finite. Hence, undoped silicon which is exposed on the sidewalls of a vertical trench is unintentionally removed from the vertical trench sidewalls. Additionally, the trench depth control, which is a critical parameter since conventional devices not utilizing SSOI rely heavily on the vertical trench for electrical isolation is achieved through the crude method of physical sputtering. This leads to a dangerous co-dependence between the lateral and vertical etch components.
The effect upon etching of doped silicon oxide is described in the three references 1–3 including two articles and portions of the text of a book cited below.    1. Ho, C. P., Plummer, J. D “Si/SiO2 Interface Oxidation Kinetics: A Physical Model for the Influence of High Substrate Doping Levels: I. Theory,” Journal of the Electro-chemical Society: Solid-State Science and Technology, p. 1516 (September 1979).    2. Ho, C. P., Plummer, J. D. “Si/SiO2 Interface Oxidation Kinetics: A Physical Model for the Influence of High Substrate Doping Levels: II. Comparison with Experiment and Discussion,” Journal of the Electrochemical Society: Solid-State Science and Technology, p. 1523 (September 1979).    3. Wolf, S., Tauber, R. N. “Silicon Processing for the VLSI Era: Volume 1—Process Technology,” Lattice Press, California, 2nd Edition (2000) ISBN 0-9616721-6–1.
Selective Silicon-On-Insulator (SSOI) methods include diverse methods of preferentially isolating device regions in addition to the device-to-device isolation utilized by the respective technology (i.e. Shallow-Trench Isolation (STI), LOCal-area Oxidation of Silicon (LOCOS), etc.). In the current state of the art, there are 3-Dimensional (3D) control issues that could prevent SSOI methods from being implemented in sub-90 nm technology nodes, unless some inherent problems are overcome, as will be manifest from the following discussion.
FIGS. 1A–1H illustrate some of the processing steps of a prior art method leading to the formation of an SSOI device 8 with a vertical trench 18T formed in a lightly doped silicon, semiconductor substrate with lateral trenches 18LT extending the sides of the vertical trench as shown in FIG. 1H.
Referring to FIG. 1A, the first step in forming a device 8 is to start with a bulk monocrystalline silicon substrate 9 which has been lightly doped with a dopant, preferably a P-type dopant, although it could be N-type dopant. Then the top surface of the substrate 9 is blanketed with a pad layer 10 that is preferably composed of silicon oxide (SiO2). Then a pad nitride layer 13 (where nitride refers to silicon nitride (Si3N4)) was deposited as a blanket onto the pad oxide film 10. Next a photoresist (PR1) mask 51 was formed on the surface of the pad nitride layer 13. The PR1 mask 51 has been patterned photolithographically with a window(s) 51W therethrough exposing a portion(s) of the top surface of the blanket pad nitride layer 13. The window 51W exposes a portion of the top surface of the pad nitride layer 13.
FIG. 1B shows the device 8 of FIG. 1A after the window 51W has been extended down to the top surface of the substrate 9 by etching an opening(s) through the pad nitride 13 layer, thereby forming a patterned implant mask 13M, followed by etching an opening(s) through the pad oxide film 10 to create a patterned pad oxide structure 10′ with the window 51W extending therethrough down to expose the top surface of the substrate 9. Opening of the window 51W through the pad oxide layer 10 at this point is an option which may be deferred until after implantation of ions 14N as illustrated in FIG. 1C.
FIG. 1C shows the device 8 of FIG. 1B after stripping photoresist mask 51. More particularly, FIG. 1C shows substrate 9 after formation of a lateral heavily doped or preferably counterdoped heavily doped lateral region(s) 14 (doped with N-type dopant) therein extending to a shallow depth in the surface of the substrate 9. The lateral, heavily N− counterdoped (P− doped), region 14 shown in FIG. 1C is formed where a lateral trench(es) is to be formed in preparation for creation of a lateral isolation region(s) of the kind shown in FIG. 1G. The term Lateral Isolation Region refers to a nonconducting volume within a semiconductor substrate to be filled with an isolating dielectric material that defines the bottom border of device source/drain (S/D) regions. In FIG. 1C a heavy dose of N type dopant ions 14N are shown being implanted into the top surface of the substrate 9 to a shallow depth, as described in U.S. patent application Ser. No. 10/604,102 of Steegan et al., the teachings thereof are incorporated herein by reference. Next, FIG. 1D shows the device 8 of FIG. 1C after the shallow implant of ions 14N has been completed followed by a subsequent anneal. Then the implant mask 13M (pad nitride) and remaining pad oxide 10′ have been stripped exposing the top surface of the substrate 9 including the top surface of the lateral, heavily doped region 14.
Next, FIG. 1E shows the device 8 of FIG. 1D after a blanket silicon layer 11 was grown epitaxially (hereinafter referred to as epitaxial silicon layer 11) with uniform thickness over the top surface of device 8 thereby burying both the lightly-doped substrate 9 and lateral, N− heavily doped region(s) 14, with equal thicknesses of epitaxial silicon.
FIG. 1F shows the device 8 of FIG. 1E after preparation steps have begun preparing for formation of features comprising a vertical isolation trench 18T shown in FIG. 1G that will extend down into the bulk silicon substrate 9. First, a blanket pad oxide film 12 is grown over the epitaxial layer 11. Then a blanket CMP (Chemical Mechanical Planarization) stop layer 15 and a blanket silicon oxide hard mask layer 16 are formed over the pad layer 10. The next step is to form a second, (PR2) mask 57 (e.g. patterned photoresist) over the hard mask layer 16. The second, PR2 mask 57 has a window 57W therethrough which has been used to etch through the hard mask layer 16 and the stop layer 15. As a result, the window 17 reaches down to expose the top surface of the pad layer 10. Some processes may extend the window 57W through pad oxide film 12 providing breakthrough of the pad oxide film 12.
FIG. 1G shows the device 8 of FIG. 1F after the second, PR2 mask 57 has been stripped followed by etching through the window 57W to extend window 57W through the pad layer 10 down to the bulk silicon substrate 9. Then etching continues down into the bulk silicon substrate 9 to form a vertical isolation trench 18T aligned to intersect with the buried, lateral (i.e. laterally extending), heavily doped/counterdoped region(s) 14. The anisotropic, vertical etching stops after it has extended through the doped region(s) 14 bisecting them thereby and forming lateral heavily doped regions 14L extending laterally from the trench(es) 18T. Preferably the vertical isolation trench(es) 18T is (are) formed in the bulk silicon substrate 9 by Reactive Ion Etching (RIE). The result is that the vertical isolation trenches 18T (which are aligned with the heavily doped lateral region(s) 14 in the substrate 9 to intersect therewith) provide access to the heavily doped lateral region(s) 14 in preparation for removal of the remainder of the heavily doped silicon thereby hollowing out the remainder of the lateral regions 14L to form lateral trenches 18LT, (laterally extending trenches) buried in the substrate 9, as seen in FIG. 1H.
FIG. 1H shows the device 8 of FIG. 1G after bombardment with ions 20 combined with lateral isotropic RIE etching to achieve the final depth of the vertical trench 18 with vertical extension 22 while etching laterally to empty out the lateral heavily doped or counterdoped lateral regions 14L to form the lateral trenches 18LT extending transversely from the trench 18T. Also illustrated is the resolution loss of horizontal critical dimensions.
FIG. 2A shows a photo-micrograph of a semiconductor device after formation of a vertical trench the prior art anisotropic etching process as indicated in FIG. 1C.
FIG. 2B shows a photo-micrograph of a semiconductor device after formation of a vertical trench with a lateral trench on the right side thereof by the prior art isotropic etching process and ion bombardment as indicated in FIG. 1D. It can be seen that the pattern produced deviates significantly from the idealized pattern shown in FIG. 1D.